1. Field of the Invention
The present invention relates, generally, to a semiconductor device and a manufacturing method thereof. More particularly, the present invention is directed to a semiconductor device having a gate that has a bottom portion that is narrower than its top portion, and a method for manufacturing the same.
2. Discussion of the Related Art
As semiconductor devices become more highly integrated, the sizes of and distances between individual devices within a semiconductor device decrease. Conventional techniques for manufacturing semiconductor devices usually involve photoresist trimming and hard mask shrinking for patterning a polycrystalline silicon gate having a narrow line width. In the conventional art, gate patterning is performed using a narrowly formed mask. A gate formed by this method has a rectangular section whose length at the top and length at the bottom are almost the same. Therefore, in a short channel device the length of the top of the gate and the length of the bottom of the gate are both short.
In the production of devices required for high-speed operation, a silicide process is usually used to reduce the gate resistance. In such a silicide process, a silicide layer with a low resistance is formed by layering metals such as titanium (Ti), tungsten (W), molybdenum (Mo), tantalum (Ta), cobalt (Co), nickel (Ni), etc. on a polycrystalline silicon gate and reacting the metals with silicon using a thermal process. If the length of the top of the gate decreases, the volume of an area where the silicide layer will be formed also decreases. Thus, the gate resistance is significantly increased and becomes a problem. For example, if a device has a gate length of 100 nm, the degradation of on-wafer variation (OWV) and on-chip variation (OCV) of the gate length becomes severe.
To overcome the above problem, a notched gate has been suggested. Since, in a notched gate, the top of the gate is longer than the bottom of the gate, it is possible to manufacture a smaller short channel device with the same photolithography technology. In addition, it is possible to increase the gate sheet resistance of a notched gate compared to a general rectangular gate having the same length at its top and bottom. The notched gate is embodied more effectively when using a gate stack made of polycrystalline silicon and silicon germanium, and has the advantage of decreasing OWV and OCV degradation.
FIG. 1 is a cross-sectional view of a notched gate in a general MOSFET structure after patterning. As shown in FIG. 1, if a T-shaped notched gate 20 is formed by forming a gate dielectric layer 15 on a semiconductor substrate 10, then an ion implantation 40 is used to form a source and a drain, the ion implantation is shadowed by the gate edge 50.
Accordingly, an offset 80 occurs between the bottom gate edge 60 and the source/drain ion implantation region 70. This phenomenon has the advantage of reducing excess overlap of the gate and a source/drain extension (SDE) in the subsequent thermal process. However, if the overlap between the gate and the SDE region is not sufficient, the driving current is considerably reduced and the speed of switching operations of the device is decreased. Recently, shallower source/drain regions are required for deterring a short channel effect, which becomes more prominent as the size of a device decreases, and the thermal process for activating the implanted ions is used to proceed in a direction such that ion diffusion can be deterred as much as possible. Accordingly, a problem of insufficient overlap between a gate and a source/drain in a notched gate arises.
To overcome the above problem, highly oblique ion implantation is required, but the ion implantation angle is limited in a high-density device within which the interval between gates is narrow.